The present disclosure relates to semiconductor memory and data storage devices, and methods of operating memory storage devices. More particularly, there is described, an energy-efficient row driver circuit implemented in a system for programming arrays of phase change memory cells for high bandwidth.
A Phase Change Memory (PCM) cell includes a memory element of a phase change material having a first state, in which the phase change material is fully crystalline and has a minimum resistance level, a second state in which the phase change material is fully amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes a mixture of both crystalline regions and amorphous regions having intermediate resistance values.
As known, the amorphous phase of a PCM tends to have high electrical resistivity, while the crystalline phase exhibits a low resistivity, e.g., orders of magnitude lower. Due to this large resistance contrast, the change in sensing signal between fully crystalline state and fully amorphous state is quite large, permitting for the immediate multiple analog levels needed for multi-level cell (MLC) operations.
In a PCM cell set or reset operation, a larger electrical current is applied in order to melt the central portion of the cell, and if this pulse is terminated abruptly, the molten material quenches into the amorphous phase, producing a cell in the high-resistance state. The reset operation tends to be fairly current and power hungry, and thus care must be taken to choose an access device capable of delivering high current and power without requiring a significantly larger footprint than the PCM element itself.
The read operation of a PCM cell is performed by measuring the device resistance at low voltage so that the device state is not perturbed.
Typical semiconductor computer memories are fabricated on semiconductor substrates consisting of arrays of large number of physical memory cells. In general, one bit of binary data is represented as a variation of a physical or electrical parameter associated with a memory cell. Commonly used physical/electrical parameters include a threshold voltage, Vth, variation of Metal Oxide Field Effect Transistor (MOSFET) due to the amount of charge stored in a floating gate or a trap layer in nonvolatile Electrically Erasable Programmable Read Only Memory (EEPROM), or resistance variation of the phase change element in Phase-change Random Access Memory (PRAM).
Increasing the number of bits to be stored in a single physical semiconductor memory cell is an effective method to lower the manufacturing cost per bit. Multiple bits of data can also be stored in a single memory cell when variations of the physical parameter can be associated with multiple bit values. This multiple bits storage memory cell is commonly known as a Multi-Level Cell (MLC). Significant amount of effort in computer memory device and circuit designs is devoted to maximize the number of bits to be stored in a single physical memory cell. This is particularly true with storage class memory, e.g., non-volatile Flash memories commonly used as mass storage devices.
FIG. 1 illustrates an iterative write system and methodology implemented for adaptively controlling the amplitude of each programming pulse in a sequence of write-verify steps. That is, in a prior art methodology 60, to achieve multiple resistance levels in a PCM cell 50, there is applied an adaptive algorithm 65 programmed to provide current pulse governed according to formula 1) as follows:I(k+1)=I(k)+α·e(k)  1)where I( ) is the applied current for programming each bit, k is the number of the iterations for multi-level cell programming. In FIG. 2, R(k) is a sensed parameter value, e.g., sensed resistance value, determined after application of programmed current pulse, RREF is a reference value of a parameter (e.g., a desired Resistance level) value e(k) is a error correction term representing a difference 62 between the programmed (desired) resistance value for the current PCM bit R(k) and the actual determined resistance value R(k) as a result of the pulse application in the current iteration. This error correction term is weighted by a value α and fed back to the adaptive algorithm 65 to reduce the number of iterations to achieve target resistance values among the PCM cells as governed according to formula 1).
FIG. 2A particularly depicts a prior art operation of a write-verify sequence 60 for physical programming of bit values (e.g., analog states) into a PCM cell 50. As shown, the PCM cell 50 includes a bit line terminal 28 and a control access device (e.g., a transistor) 30 including one transistor terminal (e.g., source or drain) connecting the PCM and a transistor gate providing a second or wordline terminal 32. In one embodiment, voltage present at the wordline (WL) terminal 32 in the manner as shown in FIG. 2B, configures the control access device, e.g., transistor 30, to control current flow through the PCM cell as it is being programmed. In the operation of the iterative write system and methodology implemented for adaptively controlling the amplitude of each programming pulse in a write-verify sequence 60, the voltage at the wordline is first SET/RESET by application of a pulse 52 to place the cell in an initial state and, with the bitline terminal held at a constant voltage, a next pulse 54a is injected at the WL terminal 32 that is immediately followed by a read operation 55 for reading in the programmed PCM cell value resulting from the application of signal 54a injected at the wordline terminal.
Referring back to FIG. 2A the read value is evaluated according to the programmed reference parameter value, e.g., a programmed reference resistance state (Rref), and the calculated difference (e.g., error) is processed and fedback to a signal generator to provide a next pulse value shown as 54b for application to the WL terminal 32 immediately followed by a read operation 55 for reading in the programmed PCM cell value resulting from the application of signal 54b injected at the wordline terminal. If, as evaluated by processing after a read operation 55, the intended programmed reference resistance state (Rref) is not achieved, then, based on the error difference, further steps may be employed to apply a next calculated WL pulse 54c for injected at the WL terminal 32 immediately followed by the read operation 55 for reading in the programmed PCM cell value resulting from the application of signals 54c and verifying whether the programmed resistance value had been achieved. The write-verify iterative process continues executing these steps until the programmed target (Rref) parameter value, e.g., resistance, for that cell (or bit) has been reached.
It should be understood that, in the embodiment depicted in FIGS. 2A, 2B, the pulse voltages 54a, 54b, etc., can be applied to the PCM cell WL terminal 32 (while keeping the voltage at BL terminal 28 constant) or the pulse voltages 54a, 54b, etc., can be applied to the PCM cell BL terminal 28 while keeping voltage at the WL terminal 32 constant. In either application, for each iteration, the state of the memory cell is always initialized, making it highest R (fully RESET the cell) or making it lowest R (fully SET the cell), then perform iterative programming-verify operation.
The basic requirement for multiple bit storage in a semiconductor memory cell is to have the spectrum of the physical parameter variation to accommodate multiple non-overlapping bands of values. The number of bands required for an n-bit cell is 2n. A 2-bit cell needs 4 bands, a 3-bit cell needs 8 bands and so forth. Thus, the available spectrum of a physical parameter in a semiconductor memory cell is typically the limiting factor for multiple bit memory storage.
Moreover, in current iterative programming schemes, it is expensive to write many cells in parallel due to the large area overhead from the control logic. Each cell needs separate control and each iteration needs to go through a whole loop including digital to analog (DAC), analog to digital (ADC) and other control logic.
It would be highly desirable to provide an energy-efficient row driver circuit which can generate a slow ramping signal for writing to many cells in parallel without consuming too much power.